FPGA Implementation of Fast Error Correction and Detection for Memories

The higher integration technologies made it possible for accessing any device so fast that within a fraction of seconds the job can be performed. Now days fast memories exists everywhere during accessing if any error happens that has to be detected and corrected within a fraction of microseconds that is made possible with help high performance error correcting codes(ECCs) such as LDPC and Turbo Codes. The proposed paper deals with coding and decoding of EGLDPC codes using majority logic decoding mechanisms. The new control logic is developed for decoding so that error correction can be possible within 3 cycles if the transmitted code vector is error free. The implementation result shows that fast error correction prototype is possible with lower area and low power. KeywordsError Correcting Codes(ECCs), Euclidean geometry low density parity check codes( EG-LDPC), Majority logic(ML) codes, Field programmable gate array( FPGA),Verilog